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2.11BSD operating system for microcontrollers
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PostPosted: Sun Nov 13, 2016 11:07 am 
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While reading the News at SIMH's github, the first information I can read there is ".. and Serge have implemented a simulator for the Soviet mainframe BESM-6 computer.."
Afaik he currently works on an FPGA implementation of that 64bit mainframe gadget..
So Serge would be the first person I would ask for a qualified estimation whether a pdp would fit into retroBSD or LiteBSD, sure :)

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PostPosted: Sun Nov 13, 2016 1:47 pm 
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He gets around a bit, doesn't he? Maybe that's why he's often silent for weeks at a time ;)

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PostPosted: Sun Nov 13, 2016 2:11 pm 
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Yes, he does the Restoration.. :P :)

Here is the final benchmark with Pascal-S, the most precise gadget I've found.
Code:
.R PASCAL
*
*BENPA.PA/G

P A S C A L - S   COMPILER V02                        HTL-MOEDLING


    0  PROGRAM BENCH(OUTPUT);
    0  (* REAL PROGRAMMERS DON'T USE PASCAL *)
    0  CONST   N = 500;
    0  VAR     X,Y: REAL;
    0          I,J: INTEGER;
    0          A: ARRAY[1..4,1..N] OF REAL;
    0  BEGIN
    0    WRITELN("START");
    4    X := 0.01;
    7    J := 2;
   10    FOR I := 1 TO N DO
   14    BEGIN
   14      A[1,I] := X;
   21      Y := SQRT(X);
   25      A[J,I] := Y;
   32      Y := SIN(X);
   36      A[J+1,I] := Y;
   45      Y := LN(X);
   49      A[J+2,I] := Y;
   58      X := X + 0.01;
   63    END;
   64
   64    WRITELN("END");
   68    WRITELN;
   69    WRITELN("  #     X        SQRT                SIN                 N-LOG");
   73    FOR I := 1 TO 17 DO
   77    BEGIN
   77      WRITELN(I:3,"  ",A[1,I]:7:3,"  ",A[2,I],"  ",A[3,I],"  ",A[4,I]);
  123    END;
  124  END.


KOMPILATION EINWANDFREI!

START
END

  #     X        SQRT                SIN                 N-LOG
  1    0.010    9.999999999E-002    9.999833334E-003   -4.605170185E+000
  2    0.020    1.414213562E-001    1.999866669E-002   -3.912023005E+000
  3    0.030    1.732050807E-001    2.999550020E-002   -3.506557897E+000
  4    0.040    1.999999999E-001    3.998933418E-002   -3.218875824E+000
  5    0.050    2.236067977E-001    4.997916927E-002   -2.995732273E+000
  6    0.060    2.449489742E-001    5.996400647E-002   -2.813410716E+000
  7    0.070    2.645751311E-001    6.994284733E-002   -2.659260037E+000
  8    0.080    2.828427124E-001    7.991469396E-002   -2.525728644E+000
  9    0.090    2.999999999E-001    8.987854919E-002   -2.407945608E+000
 10    0.100    3.162277660E-001    9.983341664E-002   -2.302585093E+000
 11    0.110    3.316624790E-001    1.097783008E-001   -2.207274913E+000
 12    0.120    3.464101614E-001    1.197122072E-001   -2.120263536E+000
 13    0.130    3.605551275E-001    1.296341426E-001   -2.040220828E+000
 14    0.140    3.741657386E-001    1.395431146E-001   -1.966112856E+000
 15    0.150    3.872983345E-001    1.494381324E-001   -1.897119985E+000
 16    0.160    3.999999999E-001    1.593182065E-001   -1.832581463E+000
 17    0.170    4.123105625E-001    1.691823490E-001   -1.771956842E+000

.

It does it in ~3.5secs. The original PDP-8/E did it in 44secs.
The precision is fantastic!! :shock:

Btw, it does 500 calcs, we print only first 17 out, here is the upper side
Code:
  #     X        SQRT                SIN                 N-LOG
490    4.900    2.213594351E+000   -9.824526215E-001    1.589235195E+000
491    4.910    2.215851970E+000   -9.805384071E-001    1.591273932E+000
492    4.920    2.218107290E+000   -9.785261398E-001    1.593308520E+000
493    4.930    2.220360320E+000   -9.764160207E-001    1.595338978E+000
494    4.940    2.222611066E+000   -9.742082608E-001    1.597365321E+000
495    4.950    2.224859535E+000   -9.719030809E-001    1.599387566E+000
496    4.960    2.227105734E+000   -9.695007114E-001    1.601405730E+000
497    4.970    2.229349670E+000   -9.670013927E-001    1.603419830E+000
498    4.980    2.231591349E+000   -9.644053747E-001    1.605429881E+000
499    4.990    2.233830779E+000   -9.617129170E-001    1.607435899E+000
500    5.000    2.236067966E+000   -9.589242888E-001    1.609437902E+000


I've checked out the Basic, Pascal and F4 at the upper ends, until it crashed (aprox):
Code:
Language               FP Array Dim   Words/FPnum (estim)   Array in Ram (kW)
========================================================================================
Basic                  A(4, 1800)             3                 21.6
Fortran IV             A(4, 500)              3                 6
Pascal-S               A(4, 1000)             4                 16

So only Fortran seems to be built for 8kW ram max..

The precision of Basic and Fortran is at the current level of 32bit single precision, except transcendentals, where they use a simple approximation only, so at the upper side ie. the sin(5) is 3 digits precise in Basic, 4 in F4 (ie. the sin() in Basic and F4 is defined in -0.2*2pi to 0.2*2pi only, afaik). Therefore are these two faster..

The Pascal-S is still 7digits precise with sin(5), thus it uses series imho. I've seen somewhere the Pascal-S uses 35bit mantissa. That would be something like "one and half precision" as CharlieS would say.

There are 4 and 5 words FP libs written in asm floating around on paper tapes. Interesting.. :idea:

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PostPosted: Mon Nov 14, 2016 12:01 pm 
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After adding the PLL clock generator I run it at 75 MHz.
The max clock frequency allowed by current design in this XC6SLX9-2 is 78.4 MHz (no special tuning, done in Xilinx'es PlanAhead 14.7).

The Pascal-S benchmark test from above, when run 50x in loop, takes 95secs.
That is 1.9sec per loop and 44/1.9= 23x faster than the original /E.

To finalize this off-the-topic "blog" - here are the two pictures - how easy it is when you can download chips directly from the OpenCores.org :D

PS: while looking at those pictures - it actually fits into a DIL16 package..

Attachment:
PDP8AXC_SCH.JPG
PDP8AXC_SCH.JPG [ 81.97 KiB | Viewed 11959 times ]

Attachment:
PDP8AXC.JPG
PDP8AXC.JPG [ 87.78 KiB | Viewed 11959 times ]

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PostPosted: Mon Nov 14, 2016 4:55 pm 
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Very nice! So when are you going to go into manufacturing then? A complete PDP-8 on a DIP? And can you do it for me as a QFN-16? ;)

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PostPosted: Mon Nov 14, 2016 4:56 pm 
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Your next task: http://opencores.org/project,w11

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PostPosted: Mon Nov 14, 2016 5:02 pm 
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Hi Pito,

The whole FPGA thing has certainly come a long ways!

So for me ease of design, use, debug and modification become the most interesting part.

Can I have some 'none of the above' idea. And then have it up and running quickly and easily?

And much more importantly can I easily observe that the design is working as intended. And thereafter, maybe a long time later, easily modify and add to it, so I can build on and reuse the already known good parts of the original design.

And for me, at least, with no external stuff not locally supplied by me such as 'cloud services' needed or wanted.

I expect most of us think the same :).


So Pito, what is your opinion of how easy, as defined above, was your design-redesign of the PDP-8e?


My first FPGA MIPS design was tortuous and basically impossible to tell what was really happening. Sometimes it would compile and work, sometimes it would compile and not work. There was a surprise at every turn. And A LOT of time spent! Right now it works, sort of!!!! It loads from a specially formatted SD card connected to a PIC16. Maybe it works with recently manufactured SD cards?

Lots of fun :).

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PostPosted: Mon Nov 14, 2016 6:33 pm 
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@Matt: A week ago I had emailed to Walter, the w11 creator, but mailer daemon said Nope.. The Q was re SLX9 and a feasibility to squeeze the w11 into it (he did it with a bigger Spartan6 - SLX16 where it takes ~1800 slices, I've got with SLX9 only ~1400 handy).

PS: when targeting 2.11bsd - my bet is the performance of the w11a @80MHz would be somewhere around 25% of the retroBSD, of course w11 could run with up to few MB of ram, that makes the difference..

Anyway, it should work with Arty. Btw Digilent sells a small stamp pcb CMOD A7-35T with Artix7-35T for $89, it has got 44+8 io pins only, so not sure it is enough for ie 16x1M ram (16+20+6 only for ram) and other stuff too. There is 8x512K 8ns put already on that board, but that is not the best config for an PDP-11.

@Wiz: I am an Integrator. The FPGA PDP-8A design has been made by RobD, a lot of hard work. I took the source and built it (routed) for my Spartan6 and Nano Board. That is maybe 1h of work.

The work with FPGA designs of this scale is easy and quick today. I can remember my time with ViewLogic and Actel 24y back (66MHz PC), where it took ~50minutes for "place and route" only (and the FPGA was 2000 gates small).

Complete process from a change in VHDL source till running the new version inside the FPGA takes 2minutes here (synthesis, implementation, bitstream, flashing in).
It works always, no magics, rock stable design suite. I did a lot with Microblaze MCU in that FPGA this fall as well. The same as to work with Arduino (when no changes in hw you just compile C source in Eclipse-like IDE and it automatically merges the C code with the existing hw bitstream - the fpga MCU runs binary from internal bram.).

Well, not exactly, but when you know what to touch then yes. It took me a while to get familiar with the ISE design process and the various tools. Fortunately, there is a lot of good info on the web thus you just write questions into g....e search and you almost always get an answer :)

With new Vivado suite it is even simpler, I've heard :). Unbelievable powerful and easy to use tools, I must admit.
Afaik Serge does the 64bit mainframe redesign with Artix7-35 too..

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PostPosted: Tue Nov 15, 2016 2:19 pm 
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Returning back to the PDP-8 off-topic - while playing with it it seems to me it calls for an upgrade, ie.:

1. to use the internal fpga's Ram as a Rom (for the loaders for example) - that enables also the smaller fpgas to be used (which lack large internal bram)

2. to use an external 128kW Sram - for example two pieces of 8x128k AS6C1008-55PCN Sram cost $7 in total maybe (and you may get them in a sexy DIP32), the CY7C1019DV33-10ZSXI the same price but 10ns and TSOP-32, moreover the 4 bits left could be used for an error correction 8-)


That would require to implement the MS8DJ and KT8A module :?: , and to escape the Sram wires out of the fpga. Not sure how the 128kW of memory is supported by existing OS/8 and sw apps, however..

PS: from the previous swap Ramdisk experiments I still have a few 8x1M 10ns, 16x4M 55ns srams in my junk-box spare. So even PDP-11 with 4MW ram could be sourced here :)

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PostPosted: Tue Nov 15, 2016 2:52 pm 
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Hi Pito,

Calling me also. I agree.

I am thinking more along the lines of multi-PDP-8 with shared RAM portion?

Maybe app. under RetroBSD to begin?

Lots of fun :).

Wiz


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PostPosted: Tue Nov 15, 2016 2:59 pm 
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Quote:
I am thinking more along the lines of multi-PDP-8 with shared RAM portion?

HW is the easy part today. You may place 8x PDP-8 into an Artix7-35T, and they may share 250kB of internal bram.

And the OS supporting that??
Do we have such OS??
Do we have such Apps??
Who will write it (in PAL asm, btw), any volunteer ?? :)

Realistically, what could be done when talking our retrofun:

1. PDP-8
. provide computer archeology, look for interesting programs, work with high level languages,
ie. a PDP-8 Pascal based programmable pocket calculator :idea:
. implement Peek and Poke into the Pascal or Basic :)
. connect something to tty2 - ie wifi ESP8266, BT, ethernet, etc - simple networking
. elaborate the I/O bus - implement a few 12bit io ports - and then blinking a LED? :)
. create a PDP-8 with 128kW external ram
. add FPP module w/ floating point
. make a C compiler (ie. Small-C initiative http://so-much-stuff.com/pdp8/C/C.php )

2. PDP-11
. build w11a with Arty's Artix7-35T, or other listed board
. squeeze w11a into XC6SLX9 Nano board and add 1-4MW ram
. try to run 2.11bsd
. add networking, i/o, etc.
. add FPU

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PostPosted: Tue Nov 15, 2016 7:44 pm 
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Hi Pito,

My reason for suggesting that sort of setup is that many, many sensing and networking things depend on timing and the interrupt model really doesn't fit for example receiving serial bits or generating MFSK.

That said, a simple processor with a constant clock rate and easy to cycle count instructions makes the programming side very easy. Also the debugging side is very easy especially if there is one micro per timing loop sensitive task. You can debug, peek, poke and restart from the main CPU. Fault condition recovery is also easy. I had this all running.

The 'main' micro loads its coresident slaves with code and communicates VIA shared RAM.

Doing this with a FPGA is a natural fit and in fact my dual MIPS kludge had several different small micros running at the same time on the one chip. Except for the compile problems previously mentioned it all worked quite well.

I lost interest when I looked as some Xilinx code that controlled the routing with some 'instructions' I had never seen. The compiler had the means to fix my problems but the manufacturer documentation was missing.

I concluded that I wasn't in the 'in crowd'.

I was NOT happy.

Once burned, twice shy.

Still I think it IS an idea worth careful consideration.

You can do the same thing multi-CPU thing with almost any small FPGA processor. And so the timing of your tasks is right, you would probably be running assembly code at least for most of the important stuff.

Lots of fun :).

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PostPosted: Tue Nov 15, 2016 8:34 pm 
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There is a "PicoBlaze" uprocessor (few configs, ie KCPSM3 - 8bitter, 64b ram, 1k rom, uart, interrupt, i/o) :
Code:
    Supports UltraScale, Virtex-7, Kintex-7, Artix-7, Zynq and older Xilinx FPGA families
    Very small size as small as 26 slices depending on device family
    Up to 4K 18-bit instructions
    Up to 240MHz performance
    Everything in FPGA - no external components required
    Highly integrated for implementing non-time critical state machine
    Predictable fast interrupt response

An assembler is also available. That could be a candidate for your requirements. The Spartan6 I am using here has got 1400 slices and 32kW of ram - so provided a single controller would use less than 1kW of ram, you may place ~dozen of them inside the chip :)

PS: That numbers there are for the high end chips most probably - for Spartan3 or 6 divide/multiply by 3 :)

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PostPosted: Tue Nov 15, 2016 10:02 pm 
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Hi Pito,

If I recall correctly there were 1 or 2 picoblazes running on it. And some other small micros.

It has been a long time since I powered it up.

Picoblaze is a pretty impressive small processor.

I think one was doing audio.

It was fun to play with.

Now that FPGA boards are getting cheaper and more powerful, I should probably try to get it up and running on more modern hardware.

Lots of fun :).

Wiz


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PostPosted: Tue Nov 15, 2016 11:51 pm 
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@Wiz: an Xmas gift only for you :geek:

C compiler for PicoBlaze

http://sp.utia.cz/index.php?ids=results&id=pblazecc

Quote:
PicoBlaze is a simple RISC-style 8-bit processor core. The document describes the C compiler
toolchain that includes the LLVM-based C compiler, assembler, and ELF-based linker. The C
frontend supports the standard C99 syntax with GNU extensions (mainly the asm keyword). The
compiler backend uses standard target-independent optimizations such as loop unrolling, inlining, and
extensive constant propagation across loops. It supports code generation for KCPSM3, PB3A, and
KCPSM6 processors. The PicoBlaze code generator performs register allocation and simple peephole
optimizations. Function parameters are passed both in registers and on stack. Several illustrative
program examples are given in the documentation.


I've done some reading in PicoBlaze guide for my Spartan6 - it requires 32slices and 1bram when setup with 1kW of rom. That means I can place 32 of KCPSM6 inside my chip. Thus I can build a 32bit CPU with highly parallel architecture, where each PB will process its own bit of information :P

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PostPosted: Wed Nov 16, 2016 2:44 pm 
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Hi Pito,

Nice gift. Thanks.

I am wondering whether to get the board Serge got or the one you got? I would appreciate any comments you or Serge might have.

Probably time for a new toy for me for Christmas thanks to your suggestions :).

I have never gotten along well with compilers. I like the original idea that the compiler produces assembly code that I hand integrate into my code.

In the past it seems that I can reduce the original size of the compiled code to about 50% and of course it runs MUCH faster too.

Of course Linux has changed a lot of things. I seems to be getting to the point where the main CPU will 'have' to run Linux to even be of interest to anyone and it must be networked.

And Linux has become a real PIG. I have an early RedHat system still running and doing useful work on a 32meg 486DX2. How did it happen that overbloat has taken over the world so throughly?

It occured to me that some of the peripheral CPUs 'should' probably be Arduino? Lots of code that is known to work available. There are known good support tools. Just gotta get it easily connected to the main CPU. But with an FPGA, shared RAM connectivity is already there.

So back to the original question. Which dev. board should I buy and how many $$ does an adequate 'production' board cost?

Lots of fun :).

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PostPosted: Wed Nov 16, 2016 2:50 pm 
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32 meg?!?! I recall when I used to run Slackware 1.3 on machines with 4 meg!

Mind, I also had to suffer Xenix on a 386 at the same time... Man that was horrible.

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PostPosted: Wed Nov 16, 2016 3:58 pm 
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@wiz: above in my post is the detailed description of the Nano board with a link.
viewtopic.php?f=3&t=37810&start=20#p44074

Quote:
So back to the original question. Which dev. board should I buy and how many $$ does an adequate 'production' board cost?

The small XC6SLX9 boards without sram/dram cost $30-45 free shipping.
The boards with sram/dram cost 45++.
I took the smallest board I found with almost all pins escaped out as I want to use it as a "breakoutboard".

There are eval boards with a lot of stuff on them (switches, connectors, buttons, 7seg leds) - they cost 40++.

A good Xmas gift for me would be an Xilinx Virtex Ultrascale eval board for $15.9k, however..
https://www.xilinx.com/products/boards- ... 110-g.html

Btw, I've seen in a discussion someone claimed they bought an eval board from Xilinx for $600k, but I cannot find it on the web.. The listed eval systems cost $100k-200k
https://www.xilinx.com/products/boards- ... scale.html

Serge afaik is using Basys 3 from Digilent with an Artix XC7A35T-1CPG236C on it.
His fpga is 4x bigger than mine in every parameter except clock:)

NOTE: the Spartan6 maybe 7 (XC6,7) and all lower families use ISE 14.7 IDE, which is not supported by Xilinx since 10/2013. The IDE works fine however, so people use it. You will get support at Xilinxes official forum.
The newer higher models - from Artix7 upwards, are only supported by new Vivado IDE.
So you would need Vivado with Arty, Basys 3, etc.



Btw, to who can tell me how to copy a file (in win or linux) onto a DEC formatted disk (RK05) or Diskette (RX) (except with "putr.com" written in asm and running under 32bit dos only) I will put "Sir" in front of his name when communicating in writing :)

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PostPosted: Wed Nov 16, 2016 6:29 pm 
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:evil:
I finally managed to copy 130.5kB large Pascal-S source (9081 asm lines) onto an existing bootable RK05 disk (with assembler on it - I want to assemble the Pascal from source).

1. take VM Win7
2. install DOSbox
3. transfer disk.rk05 image and pascal.pa from Linux VM to DOSbox
4. run putr.com in dosbox
5. in putr mount r: disk.rk05 /rk05 /os8
6. in putr copy pascal.pa r:
7. transfer disk.rk05 to Linux VM
8. dd the disk.rk05 on the SDcard
9. boot the SDcard in PDP-8

I created a copy of pascal.pa -> pasc.pa and tried to assemble, but getting
error PH 0200, so something is missing..
Code:
..
FORT  .SV  25 07/05/93  PASCAL.PB 161 02/15/92  PASCAL.PA 340 11/16/92
LIB8  .RL  29 07/05/93  PASCAL.TX  15 02/15/92  PASC  .PA 340 11/16/92

  84 FILES IN 2642 BLOCKS -  550 FREE BLOCKS

.R PAL8
*PASC<PASC/K
PH  0200

.

The PAL8 worked with the 130kB large source on the disc for 5secs - good to have and SDcard LED handy :)

The code ends as follows - the PH error says "Phase error - either no $ appeared at the end of the program, or < and > in conditional pseudo-ops did not match.."
Code:
        DCA I (7745
        DCA I (7746     /CORRECT JOB STATUS WORD
        CDF 10          /(MAKE IT RESTARTABLE)
        TAD I (7643
        AND (20         /CHECK  /H - OPTION
        CDF CIF 0
        SZA CLA
        JMP I (7600     /RETURN TO OS8 MONITOR
        JMP I (ISTART   /START INTERPRETER

IIDEVH, 0
IIBLOCK,0
F6T0,   IDEVBUF
C1200,  -1200

        PAGE


.

Is that the end..?
Update: Added "$" at the end of the source, repeated the entire procedure, and got the same error.
Tried in simh with the same result.

_________________
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PostPosted: Wed Nov 16, 2016 10:01 pm 
Contributor

Joined: Mon Nov 12, 2012 1:34 pm
Posts: 1091
Hi Pito,

Thanks.

Hmm.... Dev system for $100k+. Board for 15.9k. Need to use old software.

I had almost convinced myself that this time Xilinx was going to be different.

Probably better to put some PICs on a PCB and call it close enough? Maybe some FPGA plug in board that more or less runs. With many voltages and other magic sauce.

Or maybe just use some big company's Linux board with other stuff attached.

It will be fun to compile Pascal from sources. You must be VERY close. Just gotta figure out the necessary magic. Those were certainly the days. Funny lines required to make 8051 assembler produce desired code, etc.

I think that simple, small and easy to use and debug is the direction to go. I hope Serge will chime in with his thoughts.

I wonder if I can do anything if I buy his FPGA board or whether it will just be another board on the junk pile?

We are certainly in a world of over bloat and lots of smoke and mirrors :).

Lots of fun :).

Wiz


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