RetroBSD

2.11BSD operating system for microcontrollers
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 Post subject: 32MZSDRAM board PCB v1.0
PostPosted: Sat Oct 05, 2013 6:58 am 
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Hi, as indicated in other topics and offline discusions, with 32mz we still need the swap placed on an external device. The 32mz can address 32MB of ram via EBI and 32MB via SQI (4pin SPI), or more via banking. Those ram spaces are mapped into 32mz's address space.

Now the discussion is about how to provide at least 8MB of swap, probably a bare minimum needed by the 32mz running retrobsd. That is key for the PCB design, probably similar to the 32MXBOARD.

So the options are:

Code:
1. SRAMs - small capacities (16x1M, 16x2M), in TQFP, 10-55ns, expensive($40/8MB)

2. PSRAMs - larger capacities (up to 16x16M), BGA only, 75ns (or faster in burst modes), cheaper (~$5/8MB) + maybe additional $5 penalty for a 4layer PCB (5x5cm)

3. SQI SRAMs, MRAMs - smallest capacities (128kB max today), in TQFP, expensive ($64-$200/8MB)

4. SDRAMs - larger capacity (16x16M), in TQFP, slower (bitbanging), cannot be mapped into the address space, cheapest ($2/8MB)


Is there any other option?

Provided we do not target running the code out of external ram with first prototypes, it seems to me the easiest way is to use the existing SDRAM concept (swap and fs on the RAMDISK, I would estimate something like 6-8MB/sec r/w speed), the second option is a BGA routing and soldering exercise (estimated speeds 15MB/sec or better)..

@Jaromir: unless somebody comes with a better option, would it be the replacing 32mx with 32mz in the current pcb design feasible? Thus we may come to something usable fast and cheap ;)

Chips required:
Code:
PIC32MZ2048ECH100-I/PF, or
PIC32MZ2048ECG100-I/PF, or
PIC32MZ1024ECH100-I/PF, or
PIC32MZ1024ECG100-I/PF


@Serge: would such board be ok for porting the retrobsd on it?

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PostPosted: Sun Oct 06, 2013 7:11 pm 
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Modifying existing board shouldn't be too difficult.
We can add SDRAM to PIC32MZ. Somebody needs to adjust the driver, though.

I looked at this PSRAM http://cz.mouser.com/ProductDetail/ISSI ... WLnPRRM%3d and the BGA package seems usable. I believe it would be even doable even at 2-layer board - I need to prove this.
I noticed TSOP package in datasheet.

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PostPosted: Sun Oct 06, 2013 8:52 pm 
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They notice, but they decided not to produce it in tsop.
Mail from Sept 2012 (my Q on IS66WVE4M16BLL tsop version availability):
Quote:
Hi Pito,
Thanks for checking again. Unfortunately 64Mb PSRAM does not have TSOP available due to very limited demand.
Best regards,
Integrated Silicon Solution, Inc.

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PostPosted: Mon Oct 07, 2013 4:28 pm 
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Study in red - IS66WVE4M16BLL-70BLI 16x4M, PSRAM 48BGA, 0.75mm pitch, 0.15mm wires,
single side routing..


Attachments:
bga mem 2.jpg
bga mem 2.jpg [ 57.42 KiB | Viewed 18556 times ]

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PostPosted: Mon Oct 07, 2013 5:12 pm 
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Looks like it's going to fail on DRC test.
I wonder what impact on solder-ability would have using smaller pads for BGA balls. This is probably the one option for passing Itead/Seeed DRC criteria (6/6 mils).

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PostPosted: Mon Oct 07, 2013 5:18 pm 
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Try it with 6mil, and pads 0.25mm dia..
And use none solder mask defined pad - the opening dia in the soldermask 0.35-0.4mm for example, so the solder will connect the pad's copper from the side edges as well.. And gold plated..
The Q is how Itead is able to align the layers :)
PS: try to place 2 of them - even I doubt it will fit on the PCB because of interconnects..

PS: Just kidding.. Imagine - one package from top and the second from bottom, on the same place.. :ugeek:

PS: And you may mess with addresses and data lines as you like... or not?? Hmm, not sure yet with PSRAM, there are some PAGE modes..
No - you can't mess as you like - because of "page read mode" - interesting for swap - hopefully mz does support it somehow..maybe..

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PostPosted: Tue Oct 08, 2013 3:15 pm 
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Btw there is an ulp called "route-bga.ulp" - maybe it works..
It works somehow:
2x 48bga packages randomly wired, pitch 0.75mm. It did first time auto, but with 4/3mil technology :evil:
route-bga.ulp tells you, based on drc params (drc must be set prior running the ulp) whether the package is routable with set drc params, then makes escapes. After that you may do standard (auto) routing..

Pads are 18mil.
BTW - is the pitch 0.75mm or 0.03 inch?? (see datasheet)


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test 2 bga.jpg
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PostPosted: Wed Oct 09, 2013 8:45 am 
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Oh, inches, ounces, foots, yards, psi's, furlongs per fortnight, beardseconds, how we all love those...

I believe pitch is 0,75mm. Imperial units doesn't seem to match, however in whole datasheet they are using metric units.
Imperial units sucks, btw.

I created Eagle component for IS66WVE4M16BLL70BL and did quick routability test. With pad size 0,33mm I'm able to do escape routing that meets Itead DRC standards. Those are 0,1524mm (imperial units sucks, did I ever mention that?) wide routes (6 mils), btw.


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PostPosted: Wed Oct 09, 2013 6:21 pm 
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Interesting tables for BGA based pcb designers :)

http://www.topline.tv/SMD_vrs_NSMD.html

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PostPosted: Thu Oct 10, 2013 12:49 pm 
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Quote:
With pad size 0,33mm I'm able to do escape routing that meets Itead DRC standards. Those are 0,1524mm .. wide routes (6 mils), btw.

I created my package with pads 12mil (0.3048mm) and 6mil (0.1524mm) routes do not pass the drc.. there is -0.006 needed to pass between the pads.
How did you pass with 0.33?

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PostPosted: Mon Oct 14, 2013 5:20 am 
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You are right. My package had mistakenly 0,8mm pitch instead of 0,75mm.
Seems like we are going to have hard time to route it with 6mils routes. 12 mils pads - still not enough - are IMHO too small. We need at least 4/4 mils PCB.

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PostPosted: Mon Oct 14, 2013 6:59 am 
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With help of my fair knowledge of Yitizi Zidian I've discovered the EBI on the 100pin version can address 1Mhalfwords (2MBytes) only, so we need 2 bits for A20 and A21, also I would connect /ZZ high (power down feature and config), UB/LB high, and A0-A4 to A0-A4 EBI mapping (for the page read mode supported by 32MZ). We do not need Ready signals as the EBI allows settings of all mem cntrl signals durations (~5bits, multiples of mcu clock period).

So directly addressable are only 2MBytes of the external sram with 100pin package. The big Q is how the EBIs pin mapping collides with other signals we maybe need. Most probably we will loose 8bits (+8data bits) against the 32MX board.

The IS66WVE4M16BLL memory can be configured with a config control word - the config word is written into its control register via the address bus with /ZZ signal, or via a "software access sequence" (writing in a special sequence to the 3FFFFFh). /ZZ pin is not needed (/ZZ high) when the deep power down mode is not required (it looses all the data in DPD).

Btw, for "swap only purposes" there is an option to have it with an "8bit data bus mode" only, and switching UB/LB (as the address n. A22) while having the data pins in parallel (8+8). In that config the memory HighZ the respective half of the data bus thus the data are not written/read.

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PostPosted: Tue Oct 15, 2013 6:39 pm 
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Any volunteer to double check? :D
What is left when the external 8MB psram is connected to (green - wires to the sram). Not much left, however..


Attachments:
PIC32MZ_sram.jpg
PIC32MZ_sram.jpg [ 68.94 KiB | Viewed 18350 times ]

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PostPosted: Wed Oct 16, 2013 6:28 pm 
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Please, share the Eagle part with us.

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PostPosted: Sun Oct 20, 2013 11:25 am 
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Hopefully we'll see your .pcb and .sch for 32mxboard and 32mzboard soon.. ;)


Attachments:
pic32mz100.rar [5.43 KiB]
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PostPosted: Tue Oct 22, 2013 1:45 pm 
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The BGAs are smaller, indeed.. Have got a lot of balls, however.. :)
16x2M Cypress sram tsop against 4x 16x4M ISSI IS66WVE4M16BLL70 bga..
PS: not only because of the package. The ISSI is a psram - internally dynamic one, with static interface. Therefore much smaller..


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