RetroBSD

Preliminary (from the websources):
- PIC32MZDA is based on the MIPS m14KEc core
- up to 128MB dram
- SDHCI - probably something like SDIO
- they talk about PIC32MZDA kit, the MIPS Technologies Malta evaluation board, "MIPS SEAD3 board"
- Linux drivers development at https://lkml.org/lkml/2015/12/14/824

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Just leaving some links here
http://www.microchip.com/forums/FindPost/888520
http://www.microchip.com/forums/m887839.aspx - the datasheet seems to be gone.

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http://jaromir.xf.cz/
https://hackaday.io/jaromir/

+1 for the last post in the link above
pic32mx/mz is an MCU..

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Hi All,

MANY years ago I suggested DDR to Microchip [ at the time of the initial PIC32 design ].

So here we are finally!

128MB seems much too small. Most Linux boards are at least 512MB or 1GB.

I wonder what their upgrade path looks like?

Real i/o pins and runs Linux? I think they should add some sort of simple ethernet type of single pin networking to their on chip feature set! Maybe a TTL level version of 10/100/1000base2?

Wiz

I have been to the source, and know a lot now, but unfortunately I can't tell you much (NDA, you see).

What I can say though is:

There are three chip formats - 169 pin BGA, 176 pin LQFP, and 288 pin BGA.

The two smaller chips have 32MB of DDR2 internally and no external interface. The 288 pin BGA has no internal DDR2 but has an external interface which supports up to 128MB of DDR2.

So it's not all hugs and puppies - if you want external DDR2 then you have to have the ability to work with high density BGA chips...

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"I was trying to find out if it was possible to only eat one Jaffa Cake. I had to abandon the experiment because I ran out of Jaffa Cakes".

I think this is more than great news. Easy to solder package (LQFP176) with 32MB of internal RAM, that sounds fantastic.

Now I'd love to know two things:
1, What is the official release date.
2, How long is the errata list.

_________________
http://jaromir.xf.cz/
https://hackaday.io/jaromir/

There's no mention in the DS if you can execute from DRAM or not. It will be detailed in section 55 of the FRM but I haven't managed to get hold of that yet.

The DRAM is really designed to be used for a framebuffer. It has the GPUs from (or similar to) the PIC24 DA chips.

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"I was trying to find out if it was possible to only eat one Jaffa Cake. I had to abandon the experiment because I ran out of Jaffa Cakes".

I have just had it confirmed, yes you can execute directly from the DDR2. It's not "designed" for that but it is "technically" possible.

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"I was trying to find out if it was possible to only eat one Jaffa Cake. I had to abandon the experiment because I ran out of Jaffa Cakes".

The execution out of ddr2 will cost you ~10-12 clock cycles, my bet.

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Hi Pito,

I wonder at what point it makes sense to copy a routine from flash to RAM and execute out of RAM.

Encryption is probably one case?

That said, seldom used library routines are probably better in flash.

It's an interesting question: How to keep the core processor(s) the most busy? How to organize things to make the best use of the slower access memory units?

Certainly init type code is often big but only run once so maybe it 'should' be in flash or even mass storage [SD]?

Lots of fun .

Wiz

That's why most processors which use external RAM are usually equipped with I-cache.

Will the ddr2 be put directly on the MCU die or will it be a piggyback solution (a stack of two independent chips)?
The broadcoms (ie. Rpi) do it as stacked, therefore they got such huge rams volumes.
Putting the 32MB ddr2 directly on a single chip together with the MCU would be something new for me, and a source of troubles, I bet.

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A few years ago Axis Communications produced the ETRAX 100LX MCM SoC with 16 MB SDRAM inside the package.
https://en.wikipedia.org/wiki/ETRAX_CRI ... _100LX_MCM
http://www.axis.com/files/datasheet/ds_ ... 505_lo.pdf

So Etrax is multichip too.
Hopefully MCHP does not go with a single chip solution..
PS: a single chip solution would be great (cheaper, more reliable) provided the vendor is able to produce a new tape every quarter, moreover with an empty errata sheet.

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For those who didn't attend Masters 2015, here is presentation I found in corner of internetz http://gamma.spb.ru/media/pdf/masters2015/N32.pdf

Seems like PIC32MZ DA should have a little bit more RAM too. 640kB of RAM should be enough for everybody.

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http://jaromir.xf.cz/
https://hackaday.io/jaromir/

I have found similar document in Latin alphabet.
http://www.microchip.com.cn/community/h ... _3/005.pdf

.. stacked 32MB dram.. I doubt you can execute from the dram,, Maybe load a chunk from dram into the sram and then execute.. It will cost a lot..

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Well if you looked that those slides it does show data and instruction caches (drawn inside the cpu core so... DDR accesses would be cached SRAM accesses probably as well thought it isn't drawn on the external bus).. it should perform OK even from DDR I would imagine.

It's designed to run Linux... not having a cache and execution from DDR would make that a no go from the get go.

Jaromir ran Linux on Microchip's atmega1284p 8bitter with a bitbanged 32MB dram just fine - thus it may work, of course ..

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I have a new toy on the way, courtesy of my mates at Microchip...



That's a development board with a PIC32MZ DA chip (BGA) with external 128MB DDR memory...

It's an A1 silicon, so buggy as hell, and the newer A2 silicon (that's not available yet) has had to change the pinout to help cure some of the bugs - so these chips are not generally available outside Microchip

Still, it'll allow me to get to grips with working with the DDR and how to enable it in LiteBSD...

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"I was trying to find out if it was possible to only eat one Jaffa Cake. I had to abandon the experiment because I ran out of Jaffa Cakes".