# MIPS instruction set

The PIC32 family instruction set complies with the MIPS32 Release 2 instruction set architecture. Refer to MIPS32 Architecture for Programmers Volume II: The MIPS32 Instruction Set at www.mips.com for more information.

Operation ++ below designates a bit concatenation.

Instruction | Description | Function | |||
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ADD | Integer Add | Rd = Rs + Rt | |||

ADDI | Integer Add Immediate | Rt = Rs + Immed | |||

ADDIU | Unsigned Integer Add Immediate | Rt = Rs +u Immed | |||

ADDIUPC | Unsigned Integer Add Immediate to PC (MIPS16e only) | Rt = PC +u Immed | |||

ADDU | Unsigned Integer Add | Rd = Rs +u Rt | |||

AND | Logical AND | Rd = Rs & Rt | |||

ANDI | Logical AND Immediate | Rt = Rs & Immed[15:0] | |||

B | Unconditional Branch (Assembler idiom for: BEQ r0, r0, offset) | PC += (signed)offset | |||

BAL | Branch and Link (Assembler idiom for: BGEZAL r0, offset) | GPR[31] = PC + 8; PC += (signed)offset |
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BEQ | Branch On Equal | if Rs == Rt then PC += (signed)offset |
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BEQL | Branch On Equal Likely | if Rs == Rt then PC += (signed)offset; else Ignore Next Instruction |
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BGEZ | Branch on Greater Than or Equal To Zero | if !Rs[31] then PC += (signed)offset |
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BGEZAL | Branch on Greater Than or Equal To Zero And Link | GPR[31] = PC + 8; if !Rs[31] then PC += (signed)offset |
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BGEZALL | Branch on Greater Than or Equal To Zero And Link Likely | GPR[31] = PC + 8; if !Rs[31] then PC += (signed)offset; else Ignore Next Instruction |
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BGEZL | Branch on Greater Than or Equal To Zero Likely | if !Rs[31] then PC += (signed)offset; else Ignore Next Instruction |
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BGTZ | Branch on Greater Than Zero | if !Rs[31] && Rs != 0 then PC += (signed)offset |
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BGTZL | Branch on Greater Than Zero Likely | if !Rs[31] && Rs != 0 then PC += (signed)offset; else Ignore Next Instruction |
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BLEZ | Branch on Less Than or Equal to Zero | if Rs[31] or Rs == 0 then PC += (signed)offset |
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BLEZL | Branch on Less Than or Equal to Zero Likely | if Rs[31] or Rs == 0 then PC += (signed)offset; else Ignore Next Instruction |
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BLTZ | Branch on Less Than Zero | if Rs[31] then PC += (signed)offset |
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BLTZAL | Branch on Less Than Zero And Link | GPR[31] = PC + 8; if Rs[31] then PC += (signed)offset |
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BLTZALL | Branch on Less Than Zero And Link Likely | GPR[31] = PC + 8; if Rs[31] then PC += (signed)offset; else Ignore Next Instruction |
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BLTZL | Branch on Less Than Zero Likely | if Rs[31] then PC += (signed)offset; else Ignore Next Instruction |
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BNE | Branch on Not Equal | if Rs != Rt then PC += (signed)offset |
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BNEL | Branch on Not Equal Likely | if Rs != Rt then PC += (signed)offset; else Ignore Next Instruction |
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BREAK | Breakpoint | Break Exception | |||

CLO | Count Leading Ones | Rd = NumLeadingOnes(Rs) | |||

CLZ | Count Leading Zeroes | Rd = NumLeadingZeroes(Rs) | |||

COP0 | Coprocessor 0 Operation | See Software User's Manual | |||

DERET | Return from Debug Exception | PC = DEPC; Exit Debug Mode |
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DI | Atomically Disable Interrupts | Rt = Status; Status.IE = 0 |
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DIV | Divide | LO = (signed)Rs / (signed)Rt; HI = (signed)Rs % (signed)Rt |
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DIVU | Unsigned Divide | LO = (uns)Rs / (uns)Rt; HI = (uns)Rs % (uns)Rt |
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EHB | Execution Hazard Barrier | Skip several cycles until execution hazards are cleared | |||

EI | Atomically Enable Interrupts | Rt = Status; StatusIE = 1 |
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ERET | Return from Exception | LL = 0; if SR[2] then { PC = ErrorEPC; SR[2] = 0; } else { PC = EPC; SR[1] = 0; } |
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EXT | Extract Bit Field | Rt = ExtractField(Rs, pos, size) | |||

INS | Insert Bit Field | Rt = InsertField(Rs, Rt, pos, size) | |||

J | Unconditional Jump | PC = PC[31:28] ++ offset«2 | |||

JAL | Jump and Link | GPR[31] = PC + 8; PC = PC[31:28] ++ offset«2 |
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JALR | Jump and Link Register | Rd = PC + 8; PC = Rs |
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JALR.HB | Jump and Link Register with Hazard Barrier | Like JALR, but also clears execution and instruction hazards | |||

JALRC | Jump and Link Register Compact (MIPS16e only) | Rd = PC + 2; PC = Rs |
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JR | Jump Register | PC = Rs | |||

JR.HB | Jump Register with Hazard Barrier | Like JR, but also clears execution and instruction hazards | |||

JRC | Jump Register Compact (MIPS16e only) | PC = Rs | |||

LB | Load Byte | Rt = (byte)Mem[Rs+offset] | |||

LBU | Unsigned Load Byte | Rt = (ubyte))Mem[Rs+offset] | |||

LH | Load Halfword | Rt = (half)Mem[Rs+offset] | |||

LHU | Unsigned Load Halfword | Rt = (uhalf)Mem[Rs+offset] | |||

LL | Load Linked Word | Rt = Mem[Rs+offset]; LL = 1; LLAdr = Rs + offset |
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LUI | Load Upper Immediate | Rt = immediate « 16 | |||

LW | Load Word | Rt = Mem[Rs+offset] | |||

LWPC | Load Word, PC relative | Rt = Mem[PC+offset] | |||

LWL | Load Word Left | See Architecture Reference Manual | |||

LWR | Load Word Right | See Architecture Reference Manual | |||

MADD | Multiply-Add | HI++LO += (signed)Rs * (signed)Rt | |||

MADDU | Multiply-Add Unsigned | HI++LO += (uns)Rs * (uns)Rt | |||

MFC0 | Move From Coprocessor 0 | Rt = CPR[0, Rd, sel] | |||

MFHI | Move From HI | Rd = HI | |||

MFLO | Move From LO | Rd = LO | |||

MOVN | Move Conditional on Not Zero | if Rt != 0 then Rd = Rs |
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MOVZ | Move Conditional on Zero | if Rt = 0 then Rd = Rs |
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MSUB | Multiply-Subtract | HI++LO -= (signed)Rs * (signed)Rt | |||

MSUBU | Multiply-Subtract Unsigned | HI++LO -= (uns)Rs * (uns)Rt | |||

MTC0 | Move To Coprocessor 0 | CPR[0, n, Sel] = Rt | |||

MTHI | Move To HI | HI = Rs | |||

MTLO | Move To LO | LO = Rs | |||

MUL | Multiply with register write | HI++LO = Unpredictable; Rd = ((signed)Rs * (signed)Rt) [31:0] |
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MULT | Integer Multiply | HI++LO = (signed)Rs * (signed)Rd | |||

MULTU | Unsigned Multiply | HI++LO = (uns)Rs * (uns)Rd | |||

NOP | No Operation | — | |||

NOR | Logical NOR | Rd = ~(Rs | Rt) | |||

OR | Logical OR | Rd = Rs | Rt | |||

ORI | Logical OR Immediate | Rt = Rs | Immed | |||

RDHWR | Read Hardware Register | Allows unprivileged access to registers enabled by HWREna register | |||

RDPGPR | Read GPR from Previous Shadow Set | Rt = SGPR[SRSCtl.PSS, Rd] | |||

RESTORE | Restore registers and deallocate stack frame (MIPS16e only) | See Architecture Reference Manual | |||

ROTR | Rotate Word Right | Rd = Rt[sa-1..0] ++ Rt[31..sa] | |||

ROTRV | Rotate Word Right Variable | Rd = Rt[Rs-1..0] ++ Rt[31..Rs] | |||

SAVE | Save registers and allocate stack frame (MIPS16e only) | See Architecture Reference Manual | |||

SB | Store Byte | (byte)Mem[Rs+offset] = Rt | |||

SC | Store Conditional Word | if LL = 1 then mem[Rs+offset] = Rt; else Rt = LL |
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SDBBP | Software Debug Break Point | Trap to Debug Exception Handler | |||

SEB | Sign-Extend Byte | Rd = (byte)Rs | |||

SEH | Sign-Extend Half | Rd = (half)Rs | |||

SH | Store Half | (half)Mem[Rs+offset] = Rt | |||

SLL | Shift Left Logical | Rd = Rt « sa | |||

SLLV | Shift Left Logical Variable | Rd = Rt « Rs[4:0] | |||

SLT | Set on Less Than | if (signed)Rs < (signed)Rt then Rd = 1; else Rd = 0 |
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SLTI | Set on Less Than Immediate | if (signed)Rs < (signed)Immed then Rt = 1; else Rt = 0 |
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SLTIU | Set on Less Than Immediate Unsigned | if (uns)Rs < (uns)Immed then Rt = 1; else Rt = 0 |
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SLTU | Set on Less Than Unsigned | if (uns)Rs < (uns)Immed then Rd = 1; else Rd = 0 |
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SRA | Shift Right Arithmetic | Rd = (signed)Rt » sa | |||

SRAV | Shift Right Arithmetic Variable | Rd = (signed)Rt » Rs[4:0] | |||

SRL | Shift Right Logical | Rd = (uns)Rt » sa | |||

SRLV | Shift Right Logical Variable | Rd = (uns)Rt » Rs[4:0] | |||

SSNOP | Superscalar Inhibit No Operation | NOP | |||

SUB | Integer Subtract | Rt = (signed)Rs - (signed)Rd | |||

SUBU | Unsigned Subtract | Rt = (uns)Rs - (uns)Rd | |||

SW | Store Word | Mem[Rs+offset] = Rt | |||

SWL | Store Word Left | See Architecture Reference Manual | |||

SWR | Store Word Right | See Architecture Reference Manual | |||

SYNC | Synchronize | See Software User's Manual | |||

SYSCALL | System Call | SystemCallException | |||

TEQ | Trap if Equal | if Rs == Rt then TrapException |
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TEQI | Trap if Equal Immediate | if Rs == (signed)Immed then TrapException |
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TGE | Trap if Greater Than or Equal | if (signed)Rs >= (signed)Rt then TrapException |
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TGEI | Trap if Greater Than or Equal Immediate | if (signed)Rs >= (signed)Immed then TrapException |
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TGEIU | Trap if Greater Than or Equal Immediate Unsigned | if (uns)Rs >= (uns)Immed then TrapException |
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TGEU | Trap if Greater Than or Equal Unsigned | if (uns)Rs >= (uns)Rt then TrapException |
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TLT | Trap if Less Than | if (signed)Rs < (signed)Rt then TrapException |
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TLTI | Trap if Less Than Immediate | if (signed)Rs < (signed)Immed then TrapException |
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TLTIU | Trap if Less Than Immediate Unsigned | if (uns)Rs < (uns)Immed then TrapException |
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TLTU | Trap if Less Than Unsigned | if (uns)Rs < (uns)Rt then TrapException |
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TNE | Trap if Not Equal | if Rs != Rt then TrapException |
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TNEI | Trap if Not Equal Immediate | if Rs != (signed)Immed then TrapException |
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WAIT | Wait for Interrupts | Stall until interrupt occurs | |||

WRPGPR | Write to GPR in Previous Shadow Set | SGPR[SRSCtl.PSS, Rd] = Rt | |||

WSBH | Word Swap Bytes Within Halfwords | Rd = Rt23..16 ++ Rt31..24 ++ Rt7..0 ++ Rt15..8 | |||

XOR | Exclusive OR | Rd = Rs ^ Rt | |||

XORI | Exclusive OR Immediate | Rt = Rs ^ (uns)Immed | |||

ZEB | Zero-extend byte (MIPS16e only) | Rt = (ubyte) Rs | |||

ZEH | Zero-extend half (MIPS16e only) | Rt = (uhalf) Rs |